The present invention relates generally to a bus arrangement which interconnects a number of modules or components in a digital system and more particularly to bus arrangements and associated methods for providing high speed, efficient digital data transfer between the modules. Implementations of the bus arrangements are contemplated at chip level, forming part of an overall integrated circuit, and are also contemplated as interconnectig discrete modules within an overall processing system.
Many bus structures and associated operating methods typically employ an address bus and a data bus wherein transactions executed on the bus structure include an address operation and an associated data operation. Normally, the address operations are transacted on the address bus and the associated data operations are transacted on the data bus in such a way that a fixed time relationship is maintained between the address and data operation of a particular transaction. In most instances, the bus structure operates in such a way that the data operation places data on the data bus during the associated address operation. As will be seen hereinafter, this fixed relationship requirement introduces inherent limitations with regard to system performance. Some prior art bus structures use a single bus for both address and data operations, in which case the data operation immediately follows the address operation i.e., another fixed time relationship.
The above described requirement for maintaining a fixed time relationship between the address and data operation of a particular transaction, in and by itself, reduces the efficiency of bus utilization, particularly with regard to the data bus. As one example of a read transaction, a CPU addresses a particular peripheral device on the address bus thereby requesting data. In this instance, the CPU typically holds the data bus while the peripheral fetches the requested data for delivery via the data bus. During this "bus hold time" the data bus is not utilized in an efficient manner since no data is transmitted. Moreover, the addressing operation is itself extended in duration by the length of the bus hold time in waiting for data to appear on the data bus. Significant bus hold times may be encountered, for example, in the case of read transactions involving peripheral devices accessing dynamic random access memory (hereinafter DRAM). As one example of a bus hold delay involving DRAM, it is well known that DRAM must be refreshed periodically in order to maintain the data stored therein. In the instance where a peripheral such as, for example, a CPU attempts to perform a read (or, for that matter, a write) during the refresh cycle, a bus hold delay is produced until such time that the refresh cycle ends. As another example of a bus hold delay involving DRAM, the CPU may attempt to access the DRAM while another peripheral is actually using the DRAM. Thus, the CPU must wait so as to introduce a bus hold delay. Read transactions, in general, introduce bus hold delays since essentially no device is capable of instantaneous response to a read request. One of skill in the art will appreciate that system performance is directly dependent upon the efficiency of bus utilization. Other types of transactions introduce bus hold delays with consequent adverse effects on system performance, as will be described.
Write transactions performed by a CPU may also introduce bus hold delays which are similar in nature to those which are introduced by read transactions. As a specific example, the head of a fixed disk must be moved to the appropriate location at which data is to be written. This write access time constitutes a bus hold delay.
"Slaving" operations serve as still another example of non-optimum bus utilization by causing bus hold delays. In particular, a master module which requests data from a slave module typically holds the address bus and the data bus at least until the slave transmits the requested data. Unfortunately, the slave module may not have the requested data immediately at hand for any number of different reasons such as, for example, its need to prepare the requested data by performing certain processing steps. For purposes herein, the term "master module" refers to the module making a request (i.e., read or write) and the term "slave module" refers to the module that is the recipient of that request.
It should be appreciated that the discussion above is not intended to cover every instance in which system performance is adversely affected by non-optimum bus utilization, but rather to give a few examples so as to clearly point out the mechanism by which the problem occurs.
In the past, digital system designers have tolerated non-optimum bus utilization by simply accepting its reduced efficiency and consequent lower data throughput. More recently, certain arrangements have emerged which provide improvement in some aspects of bus utilization. One such arrangement is the Peripheral Component Interconnect (hereinafter PCI) Bus. One of skill in the art, however, will recognize that the PCI bus does not offer a sweeping solution to the bus utilization problem. More specifically, the PCI Bus maintains the aforedescribed fixed relationship between a transaction's address and data portions such that bus hold delays continue to be encountered.
Another arrangement which is referred to as "pipelining" offers bus utilization improvement in certain situations. These certain situations necessitate that data is transferred in a system from a particular source module to a particular destination module by way of a fixed number of physical elements which make up the "pipe". The data passing through the "pipe" is processed in precisely the same manner between the two modules so as to perform a particular operation. Unfortunately, pipelining has limited value in improving bus utilization and efficiency since improvements are only realized for that particular operation which is performed by the pipeline. Improving bus utilization and efficiency in the remainder of the system therefore remain is a concern.
As processing applications continue to increase in complexity and required levels of data throughput continue to increase, future digital systems in the form of individual integrated circuits and bus interconnected discrete components will be pushed to correspondingly higher levels of performance. As will be seen hereinafter, the present invention provides bus arrangements and associated methods which contemplate heretofore unattainable performance levels through improved bus utilization efficiency within individual integrated circuits and within bus interconnected discrete module digital systems.